Vaibbhav Taraate
Logic Synthesis and SOC Prototyping
RTL Design using VHDL
Paperback Engels 2021 9789811513169
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
Specificaties
ISBN13:9789811513169
Taal:Engels
Bindwijze:paperback
Uitgever:Springer Nature Singapore
Lezersrecensies
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Inhoudsopgave
<p>Introduction.- ASIC Design and SOC prototype.- Design using VHDL & Guidelines.- Design using VHDL & Guidelines.- Design and Verification Strategies.- VHDL Design and RTL Tweaks.- ASIC Synthesis and Design Constraints.- Design optimization.- Design optimization.- FPGA for SOC Prototype.- Prototype using Single and Multiple FPGA. </p><p></p>
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